Verilog SPI Master

A SPI Master IP written in verilog which is used to output characters entered on a keypad to a serial LCD screen

Source Code Link: https://github.com/andrade824/Verilog-SPI-Master

This project consists of a custom SPI Master IP which is used to communicate with the PmodCLS serial LCD screen (it supports I2C, SPI, and UART interfaces). This project also has a keypad scanner (the exact keypad used is the Digilent PmodKYPD keypad) that scans a keypad and outputs whatever key was pressed onto the LCD.

The following modules were used in this design:

  • SPI_LCD: This is the top level module that ties the other modules together
    • keypad: This module contains the keypad scanning and control units
      • key_ctrl: State machine that controls the keypad scanning/latching and encoding
      • key_scanner: Pulls each column signal low consecutively until a button is pressed (in which case it pulls the "ken" signal low)
      • key_latch: This latches the data until it's ready to be shifted
      • key_encoder: This converted the row and column outputs to a usable ascii value for the LCD display
    • synchronizer: This synchronizes the 1KHz data_ready signal to a 250KHz clock
    • clk_div: This divides the 500KHz clock down to 1KHz and 250KHz respectively
    • lcd_ctrl: This state machine controls whether to send data to the LCD, or the clear sequence (when the clear button is pressed)
    • spi_master: Module responsible for sending data over SPI
      • spi_shift: SPI Shift register to hold incoming and outgoing data
      • spi_ctrl: Controls when and what data is sent over SPI

This project was designed to be used on the Digilent CoolRunner-II development board, but should be able to be synthesized with most CPLDs (pinouts and other constraints will obviously change). The only other thing that will need to be changed is the fact that I'm using a built-in clock divider (specific to the CoolRunner-II chips) to divide down the clock by 16 before running it into my clock divider to further divide it. When you synthesize for your own chip, the clock divider module will need to be modified for whatever clock you'll be using.